Japan's third round of new semiconductor equipment export control regulations has recently come into effect. These rules place core equipment across the entire advanced packaging supply chain onto a strict control list and mandate a case-by-case approval process; the combination of lengthy review periods and extremely high rejection rates effectively amounts to a de facto cutoff of supplies to China.
This marks a significant third-round escalation of Japan's semiconductor export controls against China, specifically addressing gaps left by earlier measures that focused primarily on front-end wafer fabrication equipment by extending strict controls to core equipment used in the advanced packaging supply chain.
First Round (July 2023): Japan placed 23 categories of advanced semiconductor manufacturing equipment-including tools for cleaning, deposition, heat treatment, lithography, etching, and inspection-under export controls, targeting equipment capable of producing logic chips at the 14nm node and below.
Second Round (2025): Further tightening and expansion of the control list, with increased restrictions on photoresists, materials, and "catch-all" controls.
Third Round (Announced May 2026; Effective August 1): On May 29, 2026, Japan's Ministry of Economy, Trade and Industry (METI) amended the lists associated with the *Foreign Exchange and Foreign Trade Act*, bringing the full suite of back-end packaging and testing equipment for advanced packaging (Chiplet, 3D stacking, CoWoS, TSV) under export controls for the first time.
Newly added key controlled items (approximately 20 major categories, primarily focused on back-end packaging and testing):
High-end die bonders
Ultra-thin wafer thinning/grinding machines
Laser dicing/stealth dicing machines (e.g., DISCO)
TSV (Through-Silicon Via) equipment
Bumping/micro-bump plating equipment
High-precision chip sorters
Hybrid bonding machines, flexible bonding equipment
Related high-end inspection equipment, etc.
Implementation rules: All exports to China are subject to individual, case-by-case licensing. Approval processes typically take 3–6 months, and industry statistics indicate application rejection rates approach or exceed 70–80%; these high barriers to approval effectively create a "quasi-cutoff" of supplies.
49748778_6.jpg
Japan's official stated rationale is to prevent cutting-edge semiconductor technology from being diverted to military applications and to ensure economic security. However, the fundamental reason lies in the passive compliance with US geopolitical alignment and the implementation of the trilateral chip alliance among the US, Japan, and the Netherlands.
In 2023, the US compelled Japan and the Netherlands to sign a trilateral semiconductor control agreement, establishing a "small yard, high fence" blockade system based on a division of labor: the US restricts EDA tools and advanced chips, the Netherlands restricts EUV lithography machines, and Japan handles equipment and materials.
The US-Japan-Netherlands coordination creates a closed loop, realizing the intent to restrict the entire industry chain-spanning design, manufacturing, packaging, and materials.
In recent years, the US realized that even without access to advanced 7nm wafers, high-performance computing chips could still be assembled by combining mature process nodes with advanced packaging (Chiplet technology), thereby bypassing the blockade on front-end manufacturing equipment. Consequently, the US pressured Japan to extend controls to the packaging and testing (OSAT) sector, effectively blocking this "alternative route" to producing high-end computing chips.
Advanced packaging is currently a critical pathway for bypassing restrictions on advanced front-end process nodes and enabling high-performance computing (via Chiplet assembly) and HBM (High Bandwidth Memory). Japan's move aims to close off this channel for "leapfrogging" the competition.
734941218488.4264.jpg
In the short term, it has become significantly more difficult to acquire new high-end Japanese equipment for newly built advanced packaging and testing lines, and after-sales service for existing equipment may face delays.
However, leading Chinese packaging and testing companies (such as JCET, Tongfu Microelectronics, and Huatian Technology) had already accelerated domestic substitution efforts prior to the implementation of these controls. Domestically produced equipment-including laser cutting systems (from Guangli Technology and Delong Laser), wafer thinning machines (Huahai Qingke), die bonders (Xinyichang), and sorting/testing equipment (Changchuan Technology and Jinhaitong)-has already entered the mass production verification or volume supply stage.
Some domestic production lines had largely completed the switch to primary domestic equipment by August 1, resulting in a relatively calm market reaction.
In the medium to long term, as the process of domestic substitution accelerates and verification cycles are compressed (shortening from 2–3 years to 6–12 months), the localization rate of packaging and testing equipment is expected to rise significantly.
Japan's advanced packaging equipment controls, which took effect on August 1, represent a targeted intensification of the semiconductor blockade against China, specifically aiming at the back-end sector where China currently holds the greatest potential for a breakthrough. Although it increases supply chain uncertainty in the short term, Chinese industries have already positioned themselves for domestic substitution; the actual impact is manageable and may even accelerate the process of achieving technological self-reliance.
